sca-ip-hdl
Design Unit List
Here is a list of all design unit members with links to the Entities they belong to:
[detail level 12]
 Cadd_roundkey
 CaesRTL Top level of AES ecryption core. This top level is intented to provide an interface to perform AES128 encryptions using the accelerator
 Caes_fsm
 Caes_round
 Cclock_mux
 Ccoarse_block
 Ccoarse_line
 Cfifo_counter
 Cfifo_ctrl
 Cfifo_fsm
 Cfifo_generator_0
 Cfine_block
 Cfine_line
 Cgamma
 Ckey_expander
 Ckey_expansion
 Ckey_expansion_fsm
 Ckey_schedule
 Cklein_top
 Cmcrypton_top
 Cmix_columns
 Cmix_prod
 Cmul_poly
 Cperm_layer
 Cpi
 Cpresent_S_AXI_top
 Cpresent_top
 Cro
 Cro_bank
 Cro_coder
 Cro_exp_sum
 Cro_output
 Crotate_mix_nibbles
 Cround_counter
 Csampling_block
 Csampling_line
 Csbox
 Csbox0
 Csbox1
 Csbox2
 Csbox3
 Cshift_rows
 Cstate_diff
 Cstate_reg
 Csub_bytes
 Csub_layer
 Csub_nibbles
 Ctau
 Ctdc
 Ctdc_bank
 Ctdc_exp_sum
 Ctdc_output