ro_arch Architecture Reference

Signals
clock_s	std_logic
last_s	std_logic
state_s	std_logic_vector ( depth_g- 1 downto 0 )

Attributes
dont_touch	count_reg : label is " true "
dont_touch	sampling_reg : label is " true "

Instantiations
oscillator	lut2
last_inv	lut1
count_reg0	fdce
count_reg	fdce
sampling_reg	fdce