Processes | |
| sums_reg | ( clock_i ) | 
Constants | |
| state_width_c | positive := state_width ( depth_g ) | 
| sum_depth_c | positive := integer ( ceil ( log2 ( real ( count_g ) ) ) ) | 
Types | |
| sum_array_t | ( 0 to count_g- 1 ) unsigned ( width_g- 1 downto 0 ) | 
| sums_matrix_t | ( 0 to sum_depth_c- 1 ) sum_array_t | 
Signals | |
| curr_sums_s | sums_matrix_t | 
| next_sums_s | sums_matrix_t |