Inherited by ro_output.
Entities | |
| ro_exp_sum_arch | architecture | 
Libraries | |
| ieee | |
| rtl | |
Use Clauses | |
| std_logic_1164 | |
| numeric_std | |
| math_real | |
| ro_pack | Package <ro_pack> | 
Generics | |
| count_g | positive := 16 | 
| depth_g | positive := 8 | 
| width_g | positive := 32 | 
Ports | |
| clock_i | in std_logic | 
| steps_i | in std_logic_vector ( count_g* state_width ( depth_g ) - 1 downto 0 ) | 
| step_o | out std_logic_vector ( width_g- 1 downto 0 ) |