sca-ip-hdl
behavioral Architecture Reference

Processes

PROCESS_5  ( clk )

Components

sub_nibbles  <Entity sub_nibbles>
rotate_mix_nibbles  <Entity rotate_mix_nibbles>
key_schedule  <Entity key_schedule>

Signals

data_state  std_logic_vector ( 63 downto 0 )
data_key_added  std_logic_vector ( 63 downto 0 )
data_nibbles_subbed  std_logic_vector ( 63 downto 0 )
data_nibbles_mixed  std_logic_vector ( 63 downto 0 )
key_state  std_logic_vector ( k- 1 downto 0 )
key_updated  std_logic_vector ( k- 1 downto 0 )
round_counter  std_logic_vector ( 4 downto 0 )
k_i  natural

Instantiations

sn  sub_nibbles <Entity sub_nibbles>
rmn  rotate_mix_nibbles <Entity rotate_mix_nibbles>
ks  key_schedule <Entity key_schedule>