Inherits coarse_line, fine_line, and sampling_line.
Inherited by tdc_bank.
Entities | |
| tdc_arch | architecture | 
Libraries | |
| ieee | |
| rtl | |
Use Clauses | |
| std_logic_1164 | |
| all | |
| tdc_pack | Package <tdc_pack> | 
Generics | |
| length_coarse_g | positive := 1 | 
| length_fine_g | positive := 1 | 
| depth_g | positive := 4 | 
Ports | |
| clock_i | in std_logic | 
| delta_i | in std_logic | 
| coarse_delay_i | in std_logic_vector ( bits_per_coarse_c- 1 downto 0 ) | 
| fine_delay_i | in std_logic_vector ( bits_per_fine_c- 1 downto 0 ) | 
| delta_o | out std_logic | 
| state_o | out std_logic_vector ( state_width ( depth_g ) - 1 downto 0 ) | 
Attributes | |
| dont_touch | string | 
| dont_touch | tdc : entity is " true " |