tdc_output_arch Architecture Reference

Processes
weights_reg	( clock_i )
weight_reg	( clock_i )

Components
tdc_exp_sum	<Entity tdc_exp_sum>

Constants
sel_width_c	positive := sel_width ( count_g )
state_width_c	positive := state_width ( depth_g )
weights_width_c	positive := weight_width ( depth_g ) * count_g
weight_width_c	positive := weight_width ( depth_g )

Types
weight_array_t	( 0 to count_g- 1 ) std_logic_vector ( weight_width_c- 1 downto 0 )
state_array_t	( 0 to count_g- 1 ) std_logic_vector ( state_width_c- 1 downto 0 )

Signals
states_s	state_array_t
next_weights_s	weight_array_t
curr_weights_s	weight_array_t
next_weight_s	std_logic_vector ( width_g- 1 downto 0 )
curr_weight_s	std_logic_vector ( width_g- 1 downto 0 )

Instantiations
weights	tdc_exp_sum <Entity tdc_exp_sum>
sum	tdc_exp_sum <Entity tdc_exp_sum>