ro_output_arch Architecture Reference

Processes
last_state_reg	( clock_i )
state_reg	( clock_i )
steps_reg	( clock_i )
step_reg	( clock_i )

Components
state_diff	<Entity state_diff>
ro_exp_sum	<Entity ro_exp_sum>

Constants
state_width_c	positive := state_width ( depth_g )

Types
state_array_t	( 0 to count_g- 1 ) std_logic_vector ( state_width_c- 1 downto 0 )

Signals
last_state_s	state_array_t
curr_state_s	state_array_t
next_steps_s	state_array_t
curr_steps_s	state_array_t
next_step_s	std_logic_vector ( width_g- 1 downto 0 )
curr_step_s	std_logic_vector ( width_g- 1 downto 0 )
steps_s	std_logic_vector ( count_g* state_width_c- 1 downto 0 )
states_s	state_array_t

Instantiations
steps	state_diff <Entity state_diff>
sum_diff	ro_exp_sum <Entity ro_exp_sum>