ro_bank_arch Architecture Reference

Components
ro	<Entity ro>
ro_coder	<Entity ro_coder>
ro_output	<Entity ro_output>

Signals
raw_state_s	std_logic_vector ( count_g* depth_g- 1 downto 0 )
coded_state_s	std_logic_vector ( count_g* state_width ( depth_g ) - 1 downto 0 )

Instantiations
sensors	ro <Entity ro>
encoders	ro_coder <Entity ro_coder>
outputs	ro_output <Entity ro_output>