tdc_bank_arch Architecture Reference

Components
tdc	<Entity tdc>
tdc_output	<Entity tdc_output>

Constants
sel_width_c	positive := sel_width ( count_g )
coarse_width_c	positive := coarse_width ( count_g )
fine_width_c	positive := fine_width ( count_g )
state_width_c	positive := state_width ( depth_g )
weights_width_c	positive := weight_width ( depth_g ) * count_g

Signals
state_s	std_logic_vector ( state_width_c* count_g- 1 downto 0 )

Instantiations
sensors	tdc <Entity tdc>
outputs	tdc_output <Entity tdc_output>