sca-ip-hdl
behavioral Architecture Reference

Processes

PROCESS_7  ( clk )

Components

sub_layer  <Entity sub_layer>
perm_layer  <Entity perm_layer>
key_schedule  <Entity key_schedule>

Signals

data_state  std_logic_vector ( 63 downto 0 )
data_key_added  std_logic_vector ( 63 downto 0 )
data_substituted  std_logic_vector ( 63 downto 0 )
data_permuted  std_logic_vector ( 63 downto 0 )
key_state  std_logic_vector ( keysize- 1 downto 0 )
key_updated  std_logic_vector ( keysize- 1 downto 0 )
round_counter  std_logic_vector ( 4 downto 0 )

Instantiations

sl  sub_layer <Entity sub_layer>
pl  perm_layer <Entity perm_layer>
ks  key_schedule <Entity key_schedule>