▼ ip_repo | |
▼ aes_1.0 | |
▼ src | |
▼ round | |
add_roundkey.vhd | XOR between data block and round key |
mix_columns.vhd | LUT-style mix columns operation |
shift_rows.vhd | AES shift rows |
sub_bytes.vhd | LUT-style sub-bytes operation |
▼ rtl | |
aes.vhd | Top level wrapper |
aes_fsm.vhd | Top level FSM |
aes_round.vhd | Top level for round combinatorial |
key_expander.vhd | Key expansion top level combinatorial |
key_expansion.vhd | Top level for key expansion |
key_expansion_fsm.vhd | FSM for the key expansion |
▼ thirdparty | |
crypt_pack.vhd | Utilities package for crypto-algorithms |
mix_prod.vhd | Mix column Gallois field product for an AES state column |
round_counter.vhd | AES round counter |
state_reg.vhd | Synchronous register for round and key data block |
test_pack.vhd | NIST test values for AES algorithm |
▼ tdc_bank_1.0 | |
▼ src | |
clock_mux.vhd | Multiplixer 4 to 1 to select delayed clock |
coarse_line.vhd | Coarse delay block, providing a large amount of delay |
fine_block.vhd | Fine delay block, providing a small amount of delay |
sampling_block.vhd | Delay line block with intermediate 4-bit output |
sampling_line.vhd | Serial assembly of sampling blocks |
tdc.vhd | FIFO acquisition controller to synchronize acquisition with crypto-algorithm |
tdc_bank.vhd | Assembly of multiple TDC |